Following the overall trend in electronic design, more and more of embedded system development is being pushed onto silicon. To justify skyrocketing mask-set costs, it is becoming necessary that these ASIC designs be used across multiple products. That is why many system-on-a-chip (SOC) designs are targeted at high-volume markets-either across multiple applications (application-specific standard products) or in consumer/mobile applications with high-volume and stringent power requirements.
To achieve the required flexibility and programmability needed to deploy an ASIC in numerous products, many designers are integrating general-purpose processors directly into the ASIC design.
The embedded communications arena is experiencing this same shift in a slightly different way. There has been an explosion in design starts for the Internet infrastructure, but the compressed design cycles demanded by the Internet are driving designers to use off-the-shelf intellectual property (IP) wherever possible. Fortunately, a rich set of standard communications IP (for Ethernet, for example) is now available within specialized processors tailored for communications processor cores like the MPC8260. Instead of using general-purpose processors, embedded communication designers are pairing these powerful communication processors with their own ASIC designs. The problem is the hardware and software interface between these large, sophisticated chips, which has proven extremely complex and difficult to debug.
The trend toward incorporating processors into embedded ASIC design directly impacts verification, making it a much longer and more challenging process. A satisfactory approach for modeling and verifying these extremely challenging systems has been elusive. Meanwhile, demand for a comprehensive modeling solution continues to mount as time-to-market pressures intensify and the cost of failure explodes due to expensive fabrication.
What is needed is a way to simulate the software running against the custom chip in simulation. Only in simulation can you get the required level of visibility and control to properly verify and debug the hardware/software interface. Waiting to verify the interaction until the chip reaches a physical prototype is too late in the design cycle. If something is indeed wrong with the embedded system, it is extremely costly and time-consuming to rectify the problem at this stage in the process. The design team can elect to fix the problem in one of two ways. First, it can choose the workaround route, which usually means moving functionality from the hardware into the software, resulting in less-than-optimal performance. Or second, it can opt to respin the ASIC, meaning it will get to market much later than desired.
The verification problem is especially acute in embedded communication products that rely on advanced processors. The processor core itself, say the MPC8260, is fairly straightforward to simulate in these applications. What makes the verification task so complex is the surrounding circuitry. The peripheral circuitry typically includes super-fast Ethernet ports, multiple bidirectional serial ports, PCI buses, LCD screen-drivers and even SAR outputs, among others. With all that functionality, there are thousands of different software states that need to be examined to fully exercise and verify these systems. The lack of sufficiently accurate models for simulation has, however, made it virtually impossible to perform useful verification before physical prototype.
One way to circumvent the verification problem for embedded designs that integrate a general-purpose or communications processor is to use FPGAs instead of ASICs. This approach significantly lowers manufacturing costs while providing a flexible environment for making modifications. Unfortunately, advanced embedded systems demand much more density than today's FPGAs can deliver, especially when a processor core is included.
A modified approach is to rely on FPGAs just for assessing system performance before first silicon and then casting the design in silicon once verification is complete. Using FPGAs as a verification test bench does, unfortunately, have some drawbacks. Putting a large design into FPGAs is difficult, but it is even more painful moving it back to the ASIC flow afterward, especially with respect to timing. Designers are also denied critical visibility into the flow of software in the processor core during verification.
To provide a more comprehensive solution, tools are now emerging that enable both the hardware and software teams to thoroughly verify complex embedded systems before committing to a physical prototype and without having to rely on FPGAs. This co-verification environment enables the hardware and software teams to use each other's work throughout the design cycle to ensure that the overall embedded system will meet its design goals.
Take the embedded communications challenge, for example. Here, this innovative solution provides the best of both worlds by combining the accuracy of hardware modeling with the speed and visibility of simulation, using a processor model as the link between the hardware and software worlds. It models the communications processor using an instruction set simulator (ISS) in place of the actual silicon core. This gives designers a clear view into the internal operations of the core. Then a hardware modeler is used in conjunction with the ISS to precisely model the detailed activity of the surrounding circuitry. A bus-functional model, a hardware model and an initialization memory model are in a high-level modeling language such as Verilog executed by the simulator. The ISS is in C, linked to the bus-functional model.
With its unique combination of a hardware modeler and a software simulator, this co-verification-modeling environment creates a fast, realistic modeling solution for embedded applications that include ASICs and processors. Now it is possible for the software team to run its code on an extremely accurate circuit description throughout the development cycle. At the same time, the hardware designers have direct access to the latest software to generate the type of intricate behavior they need to thoroughly exercise the complex peripheral environment.
Using this co-verification environment, embedded system designers of all kinds can now move their challenging processor-based designs to market much faster. In addition, their ability to see into the system's operation before the physical prototype stage dramatically improves the design's chances of first-pass success.
Baggio WANG FAN
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